In the field of modern integrated circuit devices, there is an increasing drive for the opportunity to use higher operating frequencies during high activity use-cases, and lower power consumption during low activity use-cases. In order to achieve the high operating frequencies during high activity use-cases, an integrated circuit device is required to be implemented using high operating frequency fabrication processes. However, such high frequency fabrication processes result in high power leakage of the bitcells, thereby making it difficult to achieve the required low power consumption during low activity use-cases.
For integrated circuit devices comprising applications that require access to data stored within external data storage devices, it is known to provide an on-die buffer into which data may be loaded during central processing unit (CPU) active periods. During subsequent CPU inactive periods, when the CPU and those components required for accessing the external data storage devices are powered-down, to reduce the power consumption of the integrated circuit device, the on-die buffer may remain powered-up to allow the loaded data to be accessed by other on-die modules. However, a problem with this known approach is that such on-die buffers have high power leakage, thereby limiting the reduction in power consumption that is achievable when they remain powered-up during CPU inactive periods.